A Compact 5 GHz Power Amplifier Using a Spiral Transformer for Enhanced Power Supply Rejection in 180-nm CMOS Technology

被引:2
|
作者
Choe, Young-Joe [1 ]
Nam, Hyohyun [1 ]
Park, Jung-Dong [1 ]
机构
[1] Dongguk Univ, Div Elect & Elect Engn, Seoul 04620, South Korea
关键词
CMOS; power amplifier; power supply rejection ratio; wireless; DESIGN;
D O I
10.3390/electronics8091043
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
We present a compact 5 GHz, class A power amplifier (PA) applicable for a wireless combo-chip that supports multiple radio systems in 180 nm CMOS technology. The proposed two-stage linear PA consists of a cascode input stage with a transformer-based balun, combined with a balancing capacitor as the load, where the single-ended signal is converted into the balanced output and a second-stage, class A push-pull amplifier with another transformer-based balun, which efficiently combines the output power differentially to drive a single-ended 50 Omega load. The proposed single-ended PA with an internal balanced configuration can achieve a power supply rejection ratio of 9.5 to 65.9 dB at 0.1 to 3.5 GHz, which is around a 12 to 37 dB improvement compared to a conventional single-ended PA with the same power gain. The results show that the proposed PA has a gain of 15.5 dB, an output-referred 1 dB gain compression point of 13 dBm, an output intercept point of 22 dBm with a 5 MHz frequency offset, an output saturated power of 15.4 dBm, and a peak power-added efficiency of 15%. The implemented PA consumes a DC current of 72 mA under 1.8 V supply. The core chip size is 0.65 mm(2) without pads.
引用
收藏
页数:9
相关论文
共 50 条
  • [31] A 5.8 GHz 1 V linear power amplifier using a novel on-chip transformer power combiner in standard 90 nm CMOS
    Haldi, Peter
    Chowdhury, Debopriyo
    Reynaert, Patrick
    Liu, Gang
    Niknejad, Ali M.
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2008, 43 (05) : 1054 - 1063
  • [32] A 3.5-9.5 GHz Compact Digital Power Amplifier with 39.3% Peak PAE in 40nm CMOS Technology
    Qian, Huizhen Jenny
    Liang, Jian Orion
    Luo, Xun
    2015 IEEE International Wireless Symposium (IWS 2015), 2015,
  • [33] 3-5 GHz CMOS Power Amplifier in 130nm CMOS for UWB Applications
    El-Feky, Nagham G.
    Ellaithy, Dina M.
    Fedawy, Mostafa
    2022 9TH INTERNATIONAL CONFERENCE ON ELECTRICAL AND ELECTRONICS ENGINEERING (ICEEE 2022), 2022, : 32 - 35
  • [34] A 60 GHz transformer-coupled neutralized low power CMOS power amplifier
    Chen, Bo
    Shen, Li
    Gao, Jianjun
    MICROWAVE AND OPTICAL TECHNOLOGY LETTERS, 2015, 57 (11) : 2487 - 2491
  • [35] An 8-15 GHz CMOS Power Amplifier with a Compact Transformer-based Output Combiner
    Huang, Siwei
    Dou, Bingfei
    Song, Jiajin
    Li, Xiao
    2021 THE 6TH INTERNATIONAL CONFERENCE ON INTEGRATED CIRCUITS AND MICROSYSTEMS (ICICM 2021), 2021, : 246 - 249
  • [36] A 28GHz RF Phase Shifter with High Phase Resolution in 180-nm CMOS Technology
    Lv, Xiaojing
    Mo, Tingting
    Yu, Chang
    2020 IEEE ASIA-PACIFIC MICROWAVE CONFERENCE (APMC), 2020, : 351 - 353
  • [37] Design of a 1.7-GHz low-power delay-fault-testable 32-b ALU in 180-nm CMOS technology
    Chatterjee, B
    Sachdev, M
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2005, 13 (11) : 1296 - 1304
  • [38] A 1.9-GHz cmos power amplifier using an interdigitated transmission line transformer
    Park, Changkun
    Baek, Sang-Hyun
    Ku, Bon-Hyun
    Hong, Songcheol
    MICROWAVE AND OPTICAL TECHNOLOGY LETTERS, 2007, 49 (12) : 3162 - 3166
  • [39] A 2.4 GHz Low Power Low Phase-Noise Enhanced FOM VCO for RF Applications Using 180 nm CMOS Technology
    Sachan, Divyesh
    Kumar, Harshbardhan
    Goswami, Manish
    Misra, Prasanna Kumar
    WIRELESS PERSONAL COMMUNICATIONS, 2018, 101 (01) : 391 - 403
  • [40] A 2.4 GHz Low Power Low Phase-Noise Enhanced FOM VCO for RF Applications Using 180 nm CMOS Technology
    Divyesh Sachan
    Harshbardhan Kumar
    Manish Goswami
    Prasanna Kumar Misra
    Wireless Personal Communications, 2018, 101 : 391 - 403