Void free filling of TSV vias by bottom up copper electroplating for wafer level MEMS vacuum packaging

被引:0
|
作者
Xu, Chunlin [1 ]
Wang, Xuefang [1 ]
Wang, Yuzhe [1 ]
Xu, Minghai [1 ]
Hu, Chang [1 ]
Liu, Sheng [1 ]
机构
[1] Huazhong Univ Sci & Technol, Inst Microsyst, Stat Key Lab Digital Mfg Equipment & Technol, Sch Mech Sci & Engn, Wuhan 430074, Peoples R China
关键词
FABRICATION;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Through silicon via (TSV) is an emerging technology for MEMS packaging for MEMS packaging. 370 mu m deep TSV vias with diameter of 60 mu m were filled by bottom up copper electroplating with copper methylsulfonate and methane sulfonic acid as base electrolyte. Insulating layer of the wafer was silicon nitride deposited by LPCVD. The TSV vias filling processes include electroplating to fill the vias and wet etching to remove the seed layer and adhesion layer. Patterned photoresist mask was adopted to obtain ideal electroplating results and protect the copper in the vias during the wet etching process. The copper filled wafer with silicon nitride was bonded with Pyrex_7740 glass having cavities by anodic bonding. The results of Helium pressure tests showed that the leak rate was less than 3*10(-9) Pa . m(3)/s. The results suggested the potential of TSV application in wafer level MEMS vacuum packaging.
引用
收藏
页码:64 / 67
页数:4
相关论文
共 50 条
  • [21] Local sealing of high aspect ratio vias for single step bottom-up copper electroplating of through wafer interconnects
    Saadaoui, M.
    Wien, W.
    Zeiji, H. V.
    Schellevis, H.
    Laros, M.
    Sarro, P. M.
    2007 IEEE SENSORS, VOLS 1-3, 2007, : 974 - 977
  • [22] Low-Cost Wafer-Level Vacuum Packaging for MEMS
    Roland Gooch
    Thomas Schimert
    MRS Bulletin, 2003, 28 : 55 - 59
  • [23] Wafer Level Vacuum Packaging with Al-Ge bonding for MEMS
    Don, Cheam Daw
    Jae-Wung, Lee
    Bangtao, Chen
    Singh, Navab
    2017 IEEE 19TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE (EPTC), 2017,
  • [24] Low-cost wafer-level vacuum packaging for MEMS
    Gooch, R
    Schimert, T
    MRS BULLETIN, 2003, 28 (01) : 55 - 59
  • [25] 3D MEMS High Vacuum Wafer Level Packaging
    Nicolas, S.
    Caplet, S.
    Greco, F.
    Audoin, M.
    Baillin, X.
    Fanget, S.
    2012 IEEE 62ND ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2012, : 370 - 376
  • [26] Wafer-Level Vacuum Sealing for Packaging of Silicon Photonic MEMS
    Joa, Gaehun
    Edinger, Pierre
    Bleiker, Simon J.
    Wang, Xiaojing
    Takabayashi, Alain Yuji
    Sattari, Hamed
    Quack, Niels
    Jezzini, Moises
    Verheyen, Peter
    Stemme, Goran
    Bogaerts, Wim
    Gylfason, Kristinn B.
    Niklaus, Frank
    SILICON PHOTONICS XVI, 2021, 11691
  • [27] Bottom-Up Copper Filling of Millimeter Size Through Silicon Vias
    Josell, D.
    Menk, L. A.
    Hollowell, A. E.
    Blain, M.
    Moffat, T. P.
    JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 2019, 166 (01) : D3254 - D3258
  • [28] Experimental studies of through-wafer copper interconnect in wafer level MEMS packaging
    Choa, Sung-Hoon
    Fracture and Damage Mechanics V, Pts 1 and 2, 2006, 324-325 : 231 - 234
  • [29] A FAST AND CMP-FREE TSV PROCESS BASED ON WAFER-LEVEL LIQUID-METAL INJECTION FOR MEMS PACKAGING
    Gu, Jiebin
    Liu, Bingjie
    Yang, Heng
    Li, Xinxin
    2016 IEEE 29TH INTERNATIONAL CONFERENCE ON MICRO ELECTRO MECHANICAL SYSTEMS (MEMS), 2016, : 569 - 572
  • [30] High Vacuum Wafer Level Packaging for High-value MEMS Applications
    Nicolas, S.
    Greco, F.
    Caplet, S.
    Coutier, C.
    Dressler, C.
    Audoin, M.
    Baillin, X.
    Dehag, G.
    Souchon, F.
    Fanget, S.
    2014 IEEE 64TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2014, : 1714 - 1721