Systematic Design of 10-bit 50MS/s Pipelined ADC

被引：0

作者：

Zhu, Kehan ^{[1
]}

Balagopal, Sakkarapani ^{[1
]}

Saxena, Vishal ^{[1
]}

机构：

[1] Boise State Univ, Dept Elect & Comp Engn, Boise, ID 83725 USA

来源：

2013 IEEE WORKSHOP ON MICROELECTRONICS AND ELECTRON DEVICES (WMED) | 2013年

关键词：

Pipelined ADC; SNR; ENOB; SFDR; CMOS ADC;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A systematical design analysis of a 10-bit 50MS/s pipelined ADC is presented. With an opamp-sharing technique, the power consumption is reduced drastically. Simulated in a 130-nm CMOS process, it achieves a 58.9dB signal-to-noise ratio (SNR), a 9.3 effective number of bits (ENOB), 64dB spurious free dynamic range (SFDR) with a sinusoid input of 4.858-MHz 1-V-pp at 50MS/s, and consumes less than 24 mW from a 1.2-V supply.

引用

页码：17 / 20

页数：4

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