An exploration of the technology space for multi-core memory/logic chips for highly scalable parallel systems

Chip-level multi-processing, where more than one CPU "core" share the same die with significant parts of the memory hierarchy, is appearing with increasing ftequency as standard design practice. This paper takes a broader look at how such mixed logic/memory dies may evolve in the future by walking through the latest CMOS roadmap projections, and casting them in terms of the key chip-level system level building blocks. Given the increasing importance of memory density in such systems, especially as we move to single chip-type designs, we pay particular attention to the potential use of not SRAM but leading edge DRAM for many memory structures. The roles of other factors, such as interconnect and power is also considered.