Design of IIR Digital Lattice Filter Structure using Hierarchical Folding

By using folding transformation we can determine the control circuits in digital signal processing (DSP) architectures where multiple algorithm operations are time multiplexed or folded to a single functional unit. In this paper we are focusing on reduced area, less power consumption and increased the speed of the circuit. In DSP architecture it is important to minimize silicon area so we apply folding on digital filters. The hierarchical folding transformation performs folding or synthesis only on one substructure and then completes the folding process by changing the number of switching instances and delays in the folded structure. Analytical and experimental results shows that it reduces the area and increase run time in folded architecture and hierarchical folding than original structure.