Production-Worthy WOW 3D Integration Technology Using Bumpless Interconnects and Ultra-Thinning Processes

Wafer-on-Wafer (WOW) technology for three-dimensional (3D) integration is discussed [1]. Back-to-face wafer stacking using bumpless interconnects and ultra-thinning of wafers are key features used as alternatives to conventional micro-bumps and chip-based stacking technologies [2]-[6]. There is no need for a bump process involving solder bumps and Cu posts for die-to-die internal electronic connections. Ultra-thinning of wafers down to similar to 2 mu m provides the advantage of a small form factor, not only in terms of the total volume of 3D ICs, but also the aspect ratio of through-silicon-vias (TSVs). The developed WOW process is referred to as stacking back-to-face after thinning, in which any number of thinned 300 mm wafers and/or heterogeneous dies can be integrated. This wafer stacking method is compatible with multilevel metallization in the back-end-of-line (BEOL), as if replacing dielectrics layers to thinned wafers. From an economic point of view, wafer level processing is the leading 3D process because stacking at the wafer level gives drastically increased throughput. This paper reviews WOW processes and the prospects for Tera-scale memory capacity with high energy efficiency, in contrast to conventional scaling.