Design Optimization of Tunnel FET for Dynamic Memory Applications

被引：0
|
作者：
Navlakha, Nupur [1 ]
Lin, Jyi-Tsong [2 ]
Kranti, Abhinav [1 ]
机构：
[1] Indian Inst Technol Indore, Discipline Elect Engn, Low Power Nanoelect Res Grp, Indore, Madhya Pradesh, India
[2] Natl Sun Yat Sen Univ, Dept Elect Engn, Kaohsiung 80424, Taiwan
来源：
2017 INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC) | 2017年
关键词：
DRAM; TFET; retention time; double gate;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The work reports on an innovative design to improve the scalability of misaligned Double Gate (DG) Tunnel Field Effect Transistor (TFET) for operation as dynamic memory. The design optimization is achieved through use of lateral gap on both edges of back gate (G2) that reduces Band-to-Band Tunneling (BTBT) and enhances Retention Time (RT) by a factor of 3. The front gate responsible for read mechanism can be scaled down to 75 nm while G2 can be scaled until 40 nm. The investigation highlights better scalability and improved retention characteristics.
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页数：2
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