Layered protocol wrappers for Internet packet processing in reconfigurable hardware

被引：1
|
作者：
Braun, F [1 ]
Lockwood, J [1 ]
Waldvogel, M [1 ]
机构：
[1] Washington Univ, Appl Res Lab, St Louis, MO 63130 USA
来源：
HOT INTERCONNECTS 9 | 2001年
关键词：
Asynchronous transfer mode; Circuits; Field programmable gate arrays; Hardware; Internet; Ip networks; Libraries; Protocols; Routing; Switches;
D O I：
10.1109/HIS.2001.946699
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A library of layered protocol wrappers has been developed that process Internet packets in reconfigurable hardware. These wrappers can be used with a reprogrammable network platform called the Field Programmable Port Extender (FPX) to rapidly prototype hardware circuits for processing Internet packets. We present a framework to streamline and simplify the development of networking applications that process ATM cells, AAL5 frames, Internet Protocol (IP) packets and UDP datagrams directly in hardware.
引用
收藏
页码：93 / 97
页数：5
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