Convolutional Neural Network Model Compression Method for Software-Hardware Co-Design

Owing to their high accuracy, deep convolutional neural networks (CNNs) are extensively used. However, they are characterized by high complexity. Real-time performance and acceleration are required in current CNN systems. A graphics processing unit (GPU) is one possible solution to improve real-time performance; however, its power consumption ratio is poor owing to high power consumption. By contrast, field-programmable gate arrays (FPGAs) have lower power consumption and flexible architecture, making them more suitable for CNN implementation. In this study, we propose a method that offers both the speed of CNNs and the power and parallelism of FPGAs. This solution relies on two primary acceleration techniques-parallel processing of layer resources and pipelining within specific layers. Moreover, a new method is introduced for exchanging domain requirements for speed and design time by implementing an automatic parallel hardware-software co-design CNN using the software-defined system-on-chip tool. We evaluated the proposed method using five networks-MobileNetV1, ShuffleNetV2, SqueezeNet, ResNet-50, and VGG-16-and FPGA processors-ZCU102. We experimentally demonstrated that our design has a higher speed-up than the conventional implementation method. The proposed method achieves 2.47x, 1.93x, and 2.16x speed-up on the ZCU102 for MobileNetV1, ShuffleNetV2, and SqueezeNet, respectively.