Research on software-hardware co-design methodology for video encoder design

Taking the design of video encoder for example, this paper presents a new software/hardware co-design method at high level of abstraction. We use this method to design the reduced instruction set computing (RISC) core in video encoder, and compile behavioral-level Verilog hardware-description language (HDL) of this RISC core with Synopsy's Design Compiler in 0.35 μm CMOS technology. The synthesis information of electronic design automation (EDA) tools about area, power, and timing shows that this method has the advantage of fitting special architecture into algorithms easily. Thus, use of this hardware/software co-design method can lead to raise the potential quality and shorten the development time of electronic products.