A Hardware-Based Memory-Efficient Solution for Pair-Wise Compact Sequence Alignment

A hardware-based memory-efficient sequence alignment architecture is described in this paper. This paper expresses a comprehensive blueprint of the hardware implementation of compact sequence alignment for pair-wise global alignment technique to achieve high-throughput processing. This architecture uses SRAM and only a small amount of digital logic circuitry to perform elementary operations of sequence alignment in real time. Additionally, this alignment engine does not require any preprocessing operations like in most of the existing alignment approaches do. Furthermore, it does not call for any sort of comparison mechanism for preparing final sequence alignment by the alignment co-processor. The entire architecture is simulated and synthesized in FPGA board for numerous cases considering dissimilar pseudo-randomly generated sequence pairs with variable sequence lengths ranging from 16 to 2048 nucleotides. The proposed design exhibits compact alignment of the sequences that leads to the identification of close similarity between the sequences under test. Moreover, the proposed alignment engine takes significantly less amount of time, approximate to 64-95% less time, and approximate to 85-99% less amount of memory space than existing alignment approaches. The overall system performance is studied with respect to Millions Alignments Per Second (MAPS) and exhibits approximate to 55-75% more sequence alignments of same set of DNA sequences in a stipulated time compared to existing schemes.