New Memory-Efficient Hardware Architecture of 2-D Dual-mode Lifting-Based Discrete Wavelet Transform for JPEG2000

被引:1
|
作者
Hsia, Chih-Hsien [1 ]
Chiang, Jen-Shiun [1 ]
机构
[1] Tamkang Univ, Dept Elect Engn, Tamsui, Taiwan
关键词
lifting-based discrete wavelet transform (LDWT); interlaced read scan algorithm (IRSA); low-transpose memory; 2-D 5/3 mode LDWT; 2-D 9/7 mode LDWT;
D O I
10.1109/ICCS.2008.4737288
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This work presents new algorithms and hardware architectures to improve the critical issues of the 2-D dual-mode (supporting 5/3 lossless and 9/7 lossy coding) lifting-based discrete wavelet transform (LDWT). The proposed 2-D dual-mode LDWT architecture has the advantages of low-transpose memory, low latency, and regular signal flow, which is suitable for VLSI implementation. The transpose memory requirement of the NXN 2-D 5/3 mode LDWT is 2N, and that of 2-D 9/7 mode LDWT is 4N. According to the comparison results, the proposed hardware architecture surpasses previous architectures in the aspects of lifting-based low-transpose memory size. It can be applied to real-time visual operations such as JPEG2000, MPEG-4 still texture object decoding, and wavelet-based scalable video coding.
引用
收藏
页码:766 / 772
页数:7
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