Design for testability (DFT) for RSFQ circuits

Superconducting electronics (SCE), especially Rapid Single Flux Quantum (RSFQ) logic, is being developed due to its high-performance and low power. In [1]-[3], we developed new static and delay fault models and an efficient automatic test pattern generator (ATPG) for testing both delay and static faults in RSFQ logic. However, test pattern application involves moving patterns and responses via long wires from the test equipment at room temperature to the chip under test in liquid helium. Due to the high cost associated with large numbers of such wires, testing is extremely expensive in absence of design for testability. We present a scan architecture for RSFQ circuits which enables the application of a large number of test patterns. Due to the unique characteristic of RSFQ, this scan architecture includes completely new scan cell design and a new scan control strategy. The on-chip test control logic enables scan chain to shift in test patterns from the test equipment at room temperature via a small number of wires, apply the pattern to the chip under test in parallel and at speed, and shift out the corresponding test response for checking. We demonstrate that our new scan architecture supports testing at low overheads.