A New Flip-flop Shared Architecture of Test Point Insertion for Scan Design

Since the demand for chips with high reliability is increasing, built-in self-tests (BISTs) are widely used in these days. Test point insertion (TPI) is an efficient and intuitive method to enhance the test coverage; however, due to the extra logics, increasing area overhead is inevitable. Furthermore, as growing chip size, reducing wire overhead becomes a significant problem. In this paper, a new method of TPI involving a new architecture of flip-flop (FF) shared TPI and a optimizing the test points (TPs) with considering place to reduce the area overhead. Not only hardware overhead is reduced by the new architecture, but also wire overhead is reduced by optimizing. The experimental results show reduced area overhead without significant degradation of test coverage.