Research on Hardware System of APWL Algorithm Based on FPGA

被引：0
|
作者：
Jiang Leping [1 ]
Bo Xu [2 ]
机构：
[1] Chengdu Univ Technol, Sch Mech & Elect Engn, Chengdu, Peoples R China
[2] Univ Elect Sci & Technol China, Sch Automat Engn, Chengdu, Peoples R China
来源：
2023 3RD ASIA-PACIFIC CONFERENCE ON COMMUNICATIONS TECHNOLOGY AND COMPUTER SCIENCE, ACCTCS | 2023年
关键词：
fractional calculus; fractional order; FPGA; Grunwald-Letnikov; IMPLEMENTATION;
D O I：
10.1109/ACCTCS58815.2023.00133
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
This paper proposes an improved piecewise linear based on the definition of Grunwald-Letnikov, and designs the FPGA implementation scheme of the algorithm. Compared with the previous PWL method, the main advantages of the design in this paper are that the calculation precision of fractional calculus is improved, and the consumption of FPGA hardware resources is greatly reduced. Finally, the algorithm and hardware implementation scheme are verified respectively in Matlab software and digital oscilloscope experiment platform based on FPGA.
引用
收藏
页码：728 / 738
页数：11
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