A high-speed MCML charge pump design at 10 GHz frequency in 45 nm CMOS technology for PLL application

In this paper, a new high speed two-stage charge pump is designed for phase-locked loop (PLL) application. In the proposed circuit, switch-based charge pump acts as the primary charge pump for glitch-free output, in addition to that MOS current mode logic (MCML) based faster current driving charge pump acts as the secondary charge pump. It will used to achieve the PLL locking condition quickly. MCML circuits minimize delay and perform the fast operation, hence it can be used in high frequency applications. The proposed circuit achieves very low power of 13.19 mu W with a minimum delay of 16.71 ps at 45 nm CMOS technology with a 1 V power supply in different process corners. The output noise as very low as - 232.7 dB and phase noise as - 247.2 dBc/Hz at 10 GHz frequency. The swing voltage ranges from 0 to 980 mV. Monte-Carlo simulations with 200 samples are analysed to verify the results. Finally, process voltage and temperature (PVT) analysis are performed to validate the stability of the proposed design. The simulated results shows that the proposed circuit is more stable for high-frequency PLL applications and is highly tolerant with PVT variations.