Electrical Rule Checking of Integrated Circuits using Satisfiability Modulo Theory

被引：0
|
作者：
Ferres, B. [1 ]
Oulkaid, O. [1 ,2 ,3 ]
Henrio, L. [1 ]
Khosravian, M. G. [3 ]
Moy, M. [1 ]
Radanne, G. [1 ]
Raymond, P. [2 ]
机构：
[1] Univ Lyon, CNRS, EnsL, UCBL,Inria,LIP, F-69342 Lyon 07, France
[2] Univ Grenoble Alpes, CNRS, Grenoble, France
[3] Aniah, F-38000 Grenoble, France
来源：
2023 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION, DATE | 2023年
关键词：
Electrical rule checking; Integrated Circuits; SMT solving;
D O I：
10.23919/DATE56975.2023.10137147
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
We consider the verification of electrical properties of circuits to identify potential violations of electrical design rules, also called Electrical Rule Checking (ERC). We present a general approach based on Satisfiability Modulo Theory (SMT) to verify that these errors cannot occur in a given circuit. We claim that our approach is scalable and more precise than existing analyses, like voltage propagation. We applied these techniques to a specific type of errors, the missing level shifters. On an industrial case-study, our technique is able to flag 31% of the warnings raised by the voltage propagation analysis as being false alarms.
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页数：2
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