Leakage Power Attack and Half Select Issue Resilient Split 8T SRAM Cell

There are various factors that harness the performance of an SRAM cell, out of which leakage current attackbased side-channel attack, as well as half select issue, are a major concern. Since there is a need for a circuit that could overcome both these problems at once, we propose a split 8T SRAM cell that uses split word lines unlike 6T and 8T SRAM cells. The two additional transistors like leakage power attack resilient (LPAR) 8T determine its compatibility for both cases. To demonstrate the capability of the proposed 8T cell, a comparison has been done among 6T, 8T, Split 6T and the Proposed Split 8T SRAM cell on the basis of noise margin, overlap percentage, flipping percentage, etc. Monte Carlo simulations depict the maximum overlap percentage of 96.6% for the proposed SRAM cell and a marginal time range i.e., 5.8ns for no flipping of data thus making it leakage power attack resilient as well as half-select issue free.