A 6T-3M SOT-MRAM for in-memory computing with reconfigurable arith- metic operations

被引：0
|
作者：
Jin, Xing [1 ]
Yin, Ningyuan [2 ]
Chen, Weichong [2 ]
Li, Ximing [1 ]
Zhao, Guihua [1 ]
Yu, Zhiyi [2 ,3 ]
机构：
[1] Sun Yat Sen Univ, Sch Elect & Informat Technol, Guangzhou 510006, Peoples R China
[2] Sun Yat Sen Univ, Sch Microelect Sci & Technol, Zhuhai 519082, Peoples R China
[3] Sun Yat Sen Univ, Guangdong Prov Key Lab Optoelect Informat Proc Ch, Guangzhou, Peoples R China
来源：
IEICE ELECTRONICS EXPRESS | 2023年 / 20卷 / 11期
基金：
中国国家自然科学基金;
关键词：
logic; in-memory computing (IMC); reconfigurable; SOT-MRAM; WRITE OPERATIONS; UNIT-MACRO; SRAM; ARCHITECTURE; READ;
D O I：
10.1587/elex.20.20230152
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Traditional von Neumann architecture bottlenecks such as the "memory wall" limit artificial intelligence (AI) development, and in -memory computing (IMC) as a new computing architecture can solve the above problems. Spin-orbit-torque-magnetic random access memory (SOT-MRAM) has very good advantages in IMC architecture because of its good compatibility with CMOS, high tunneling magnetoresistance (TMR) ratio, and high energy efficiency. In this paper, we propose a 6T-3M-based MRAM-IMC architecture with reconfigurable memory mode and logical operation mode. The functionality of the proposed architecture is validated using the 28 nm process design kit and the SOT-MTJ model.
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页数：5
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