Design and Analysis of a Novel Asymmetric Source Dual-Material DG-TFET with Germanium Pocket

被引:3
|
作者
Kaur, Arashpreet [1 ]
Saini, Gaurav [1 ,2 ]
机构
[1] NIT, Sch VLSI Design & Embedded Syst, Kurukshetra, Haryana, India
[2] NIT, Dept Elect & Commun Engn, Kurukshetra, Haryana, India
关键词
Asymmetric-Source; Dual-gate material structure; Ge-pocket; ON-state current; Steep subthreshold swing (SS); FIELD-EFFECT TRANSISTORS; TUNNEL-FET; GATE;
D O I
10.1007/s12633-022-02202-8
中图分类号
O64 [物理化学(理论化学)、化学物理学];
学科分类号
070304 ; 081704 ;
摘要
This article proposes a novel asymmetric source dual-material double-gate Tunnel Field-Effect Transistor with Ge-pocket (ASDM-DGTFET). The use of a Ge-pocket near the source-channel interface helps in improving the device performance by narrowing the tunnelling barrier. To boost the tunnelling field strength, a high-kappa dielectric (HfO2) is used as a gate insulator. To enhance the switching ratio, a low work function of the metal gate is used on the source side. The proposed structure outperforms both traditional TFET and asymmetric source dual-material Double Gate TFET. The impact of varying the length of the source region under the gate has also been investigated. The lowest value of subthreshold swing (SS) is observed at 65 nm of source length in the proposed device. The proposed device provides a higher ON-state current of the order of 5 x 10(-4) A/mu m, a higher figure of merit of similar to 10(12) with an average SS of 23.9 mV/dec and a point SS of 10.8 mV/dec.
引用
收藏
页码:2889 / 2900
页数:12
相关论文
共 50 条
  • [1] Design and Analysis of a Novel Asymmetric Source Dual-Material DG-TFET with Germanium Pocket
    Arashpreet Kaur
    Gaurav Saini
    [J]. Silicon, 2023, 15 : 2889 - 2900
  • [2] Analytical modeling of asymmetric hetero-dielectric engineered dual-material DG-TFET
    Dinesh Kumar Dash
    Priyanka Saha
    Subir Kumar Sarkar
    [J]. Journal of Computational Electronics, 2018, 17 : 181 - 191
  • [3] Analytical modeling of asymmetric hetero-dielectric engineered dual-material DG-TFET
    Dash, Dinesh Kumar
    Saha, Priyanka
    Sarkar, Subir Kumar
    [J]. JOURNAL OF COMPUTATIONAL ELECTRONICS, 2018, 17 (01) : 181 - 191
  • [4] Analysis of ION and Ambipolar Current for Dual-Material Gate-Drain Overlapped DG-TFET
    Kumar, Sunil
    Raj, Balwinder
    [J]. JOURNAL OF NANOELECTRONICS AND OPTOELECTRONICS, 2016, 11 (03) : 323 - 333
  • [5] Dual-Material Gate-Drain Overlapped DG-TFET Device for Low Leakage Current Design
    Kumar, Sunil
    Raj, Balwant
    Raj, Balwinder
    [J]. SILICON, 2021, 13 (05) : 1599 - 1607
  • [6] Dual-Material Gate-Drain Overlapped DG-TFET Device for Low Leakage Current Design
    Sunil Kumar
    Balwant Raj
    Balwinder Raj
    [J]. Silicon, 2021, 13 : 1599 - 1607
  • [7] Performance Assessment of GaAs Pocket-Doped Dual-Material Gate-Oxide-Stack DG-TFET at Device and Circuit Level
    Singh, Km. Sucheta
    Kumar, Satyendra
    Chaturvedi, Saurabh
    Tyagi, Kapil Dev
    Tyagi, Vaibhav Bhushan
    [J]. IET CIRCUITS DEVICES & SYSTEMS, 2024, 2024
  • [8] Partially Extended Germanium Source DG-TFET: Design, Analysis, and Optimization for Enhanced Digital and Analog/RF Parameters
    Singh, Omendra Kr
    Dhandapani, Vaithiyanathan
    Kaur, Baljit
    [J]. SILICON, 2023, 15 (03) : 1475 - 1490
  • [9] Partially Extended Germanium Source DG-TFET: Design, Analysis, and Optimization for Enhanced Digital and Analog/RF Parameters
    Omendra Kr Singh
    Vaithiyanathan Dhandapani
    Baljit Kaur
    [J]. Silicon, 2023, 15 : 1475 - 1490
  • [10] Source Material Assessment of Heterojunction DG-TFET for Improved Analog Performance
    Madan, Jaya
    Shekhar, Skanda
    Chaujar, Rishu
    [J]. 2017 INTERNATIONAL CONFERENCE ON MICROELECTRONIC DEVICES, CIRCUITS AND SYSTEMS (ICMDCS), 2017,