Partially Extended Germanium Source DG-TFET: Design, Analysis, and Optimization for Enhanced Digital and Analog/RF Parameters

Tunnel field-effect transistors have demonstrated a predominant performance in the field of semiconductors. However, low drive current and ambipolarity are major challenges for TFETs. To overcome these challenges, a Partially Extended Germaniumn source DG-TFET (PEGeDG-TFET) is proposed. This PEGeDG-TFET structure has a partially extended Ge source under the gate below the Si-epitaxial layer to improve vertical tunneling, using the overlap area concept and pocket layer to enhance lateral tunneling along with suppressed Short-Channel effect. After scaling the transistor dimension up to 40%, the proposed device performance is not only retained but greatly improved by device engineering techniques. Further, a complete metal gate contact is deployed over the Si-epi layer length and overlapping the source metal-contact over oxide width touching Si-epi layer width. The proposed device study reveals the impact of source length, dielectric material, and oxide thickness variation. It also comprehends the impact of Ge molar fraction on transfer characteristics, transconductance, RF parameters (f(t),GBP, etc). Further, the Linearity analysis in Si1-xGex source in PEDG-TFET with x varying from 0 to 1.The proposed device claims I-ON to be 3.2 mA/um, I-OFF = 3.21 x 10(-17) A/um with an I-ON/I-OFF ratio of 9.6 x 10(13) along with enhanced transconductance, cut-off frequency, and gain-bandwidth product. The potential of the proposed device for digital logic applications are examined for the worst case (equal source and drain doping), and it is demonstrated in this work along with Analog/RF applications.