Interfacial-Layer-Free Ge0.95Si0.05 Nanosheet FeFETs

被引：1

作者：

Hsieh, Wan-Hsuan ^{[1
]}

Chen, Yu-Rui ^{[1
]}

Liu, Yi-Chun ^{[1
]}

Zhao, Zefu ^{[1
]}

Lee, Jia-Yang ^{[2
]}

Tu, Chien-Te ^{[1
]}

Huang, Bo-Wei ^{[1
]}

Wang, Jer-Fu ^{[1
]}

Lee, M. H. ^{[3
]}

Liu, C. W. ^{[4
,5
]}

机构：

[1] Natl Taiwan Univ, Grad Inst Elect Engn, Taipei 10617, Taiwan

[2] Natl Taiwan Univ, Grad Sch Adv Tech nol, Inst & Undergrad Program Electroopt Engn, Taipei 10617, Taiwan

[3] Natl Taiwan Univ, Grad Sch Adv Technol, Taipei 10617, Taiwan

[4] Natl Taiwan Univ, Grad Inst Elect Engn, Grad Inst Photon & Optoelect, Dept Elect Engn, Taipei 10617, Taiwan

[5] Natl Taiwan Univ, Grad Sch Adv Technol, Taipei 10617, Taiwan

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2024年 / 71卷 / 03期

关键词：

Germanium silicon alloys; Germanium; Gallium arsenide; FeFETs; Tin; Iron; Superlattices; Chemical vapor deposition; ferroelectric field-effect transistor (FeFET); gate-all-around (GAA); GeSi; interfacial layer; isotropic wet etching; nanosheets (NSs); FIELD-EFFECT TRANSISTOR; FERROELECTRIC FET; ENDURANCE; EPITAXY;

D O I：

10.1109/TED.2024.3356444

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The substantial memory window (MW) of 1.8 V is achieved by utilizing stacked two nanosheet (NS) gate-all-around (GAA) Ge0.95 Si0.05 ferroelectric field-effect transistors (FeFETs), employing a low write voltage of 2 V. The channel phosphorus concentration similar to 1E18 cm(-3) is used to erase the absence of interfacial layer (IL) can reduce the operation voltage. An isotropic wet etching process is employed for channel release. The stacked two NSs offer the advantages of reducing cell-to-cell variation and doubling the read current. Additionally, the stability of data storage is demonstrated with the data retention of > 1E4 s, linearly extrapolated to a span of 10 years, and exhibiting high endurance >1E11 cycles. The thermal budget is as low as 400 degree celsius.

引用

页码：1758 / 1763

页数：6

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