Hardware-aware Model Architecture for Ternary Spiking Neural Networks

被引:0
|
作者
Wu, Nai-Chun [1 ]
Chen, Tsu-Hsiang [1 ]
Huang, Chih-Tsun [1 ]
机构
[1] Natl Tsing Hua Univ, Dept Comp Sci, Hsinchu, Taiwan
关键词
D O I
10.1109/VLSI-TSA/VLSI-DAT57221.2023.10134319
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper presents a hardware-aware model architecture for ternary spiking neural networks. Under realistic hardware constraints, an effective training flow is proposed with ternary model weights and quantized voltage thresholds. In addition to the enhanced output decoding of the last-50%-spike to prevent the warm-up issue, our network also incorporates a hybrid architecture by attaching two simple fully-connected artificial neural layers as the output stage. Transforming from the asymmetrical ResNeXt architecture, the proposed SNN achieves a top-1 accuracy of 90% on the CIFAR-10 dataset, with a 5.9% improvement compared to the baseline model.
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页数:4
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