Hardware-aware Model Architecture for Ternary Spiking Neural Networks

被引:0
|
作者
Wu, Nai-Chun [1 ]
Chen, Tsu-Hsiang [1 ]
Huang, Chih-Tsun [1 ]
机构
[1] Natl Tsing Hua Univ, Dept Comp Sci, Hsinchu, Taiwan
关键词
D O I
10.1109/VLSI-TSA/VLSI-DAT57221.2023.10134319
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper presents a hardware-aware model architecture for ternary spiking neural networks. Under realistic hardware constraints, an effective training flow is proposed with ternary model weights and quantized voltage thresholds. In addition to the enhanced output decoding of the last-50%-spike to prevent the warm-up issue, our network also incorporates a hybrid architecture by attaching two simple fully-connected artificial neural layers as the output stage. Transforming from the asymmetrical ResNeXt architecture, the proposed SNN achieves a top-1 accuracy of 90% on the CIFAR-10 dataset, with a 5.9% improvement compared to the baseline model.
引用
下载
收藏
页数:4
相关论文
共 50 条
  • [21] Hardware-Aware Model of Sigma-Delta Cellular Neural Network
    Aomori, Hisashi
    Naito, Yuki
    Otake, Tsuyoshi
    Takahashi, Nobuaki
    Matsuda, Ichiro
    Itoh, Susumu
    Tanaka, Mamoru
    2009 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN, VOLS 1 AND 2, 2009, : 311 - +
  • [22] HADAS: Hardware-Aware Dynamic Neural Architecture Search for Edge Performance Scaling
    Bouzidi, Halima
    Odema, Mohanad
    Ouarnoughi, Hamza
    Al Faruque, Mohammad Abdullah
    Niar, Smail
    2023 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION, DATE, 2023,
  • [23] SqueezeNext: Hardware-Aware Neural Network Design
    Gholami, Amir
    Kwon, Kiseok
    Wu, Bichen
    Tai, Zizheng
    Yue, Xiangyu
    Jin, Peter
    Zhao, Sicheng
    Keutzer, Kurt
    PROCEEDINGS 2018 IEEE/CVF CONFERENCE ON COMPUTER VISION AND PATTERN RECOGNITION WORKSHOPS (CVPRW), 2018, : 1719 - 1728
  • [24] An Affordable Hardware-Aware Neural Architecture Search for Deploying Convolutional Neural Networks on Ultra-Low-Power Computing Platforms
    Garavagno, Andrea Mattia
    Ragusa, Edoardo
    Frisoli, Antonio
    Gastaldo, Paolo
    IEEE SENSORS LETTERS, 2024, 8 (05) : 1 - 4
  • [25] FBNet: Hardware-Aware Efficient ConvNet Design via Differentiable Neural Architecture Search
    Wu, Bichen
    Dai, Xiaoliang
    Zhang, Peizhao
    Wang, Yanghan
    Sun, Fei
    Wu, Yiming
    Tian, Yuandong
    Vajda, Peter
    Jia, Yangqing
    Keutzer, Kurt
    2019 IEEE/CVF CONFERENCE ON COMPUTER VISION AND PATTERN RECOGNITION (CVPR 2019), 2019, : 10726 - 10734
  • [26] HFP: Hardware-Aware Filter Pruning for Deep Convolutional Neural Networks Acceleration
    Yu, Fang
    Han, Chuanqi
    Wang, Pengcheng
    Huang, Ruoran
    Huang, Xi
    Cui, Li
    2020 25TH INTERNATIONAL CONFERENCE ON PATTERN RECOGNITION (ICPR), 2021, : 255 - 262
  • [27] MOHAQ: Multi-Objective Hardware-Aware Quantization of recurrent neural networks
    Rezk, Nesma M.
    Nordstrom, Tomas
    Stathis, Dimitrios
    Ul-Abdin, Zain
    Aksoy, Eren Erdal
    Hemani, Ahmed
    JOURNAL OF SYSTEMS ARCHITECTURE, 2022, 133
  • [28] CHAMP: Coherent Hardware-Aware Magnitude Pruning of Integrated Photonic Neural Networks
    Banerjee, Sanmitra
    Nikdast, Mahdi
    Pasricha, Sudeep
    Chakrabarty, Krishnendu
    2022 OPTICAL FIBER COMMUNICATIONS CONFERENCE AND EXHIBITION (OFC), 2022,
  • [29] A Hardware Architecture for Image Clustering Using Spiking Neural Networks
    Aurelio Nuno-Maganda, Marco
    Arias-Estrada, Miguel
    Torres-Huitzil, Cesar
    Hugo Aviles-Arriaga, Hector
    Hernandez-Mier, Yahir
    Morales-Sandoval, Miguel
    2012 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI), 2012, : 261 - 266
  • [30] A POPULATION CODING HARDWARE ARCHITECTURE FOR SPIKING NEURAL NETWORKS APPLICATIONS
    Nuno-Maganda, Marco
    Arias-Estrada, Miguel
    Torres Huitzil, Cesar
    Girau, Bernard
    2009 5TH SOUTHERN CONFERENCE ON PROGRAMMABLE LOGIC, PROCEEDINGS, 2009, : 83 - +