Acceleration of Electromagnetic Simulations on Reconfigurable FPGA Card

被引:0
|
作者
Topa, Tomasz [1 ]
Noga, Artur [1 ]
Stefanski, Tomasz P. [2 ]
机构
[1] Silesian Tech Univ, Dept Elect Elect Engn & Microelect, PL-44100 Gliwice, Poland
[2] Gdansk Univ Technol, Fac Elect Telecommun & Informat, PL-80233 Gdansk, Poland
来源
2023 30TH INTERNATIONAL CONFERENCE ON MIXED DESIGN OF INTEGRATED CIRCUITS AND SYSTEM, MIXDES | 2023年
关键词
Field programmable gate arrays; Hardware acceleration; Scientific computing; Electromagnetics;
D O I
10.23919/MIXDES58562.2023.10203273
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this contribution, the hardware acceleration of electromagnetic simulations on the reconfigurable field-programmable-gate-array (FPGA) card is presented. In the developed implementation of scientific computations, the matrix-assembly phase of the method of moments (MoM) is accelerated on the Xilinx Alveo U200 card. The computational method involves discretization of the frequency-domain mixed potential integral equation using the Rao-Wilton-Glisson basis functions and their extension to wire-to-surface junctions. Hardware resources in our FPGA card allow for synthesizing nine independent processing paths. The implementation is evaluated in a numerical test, which involves a simulation of radiation from a monopole antenna mounted on the roof of Dodge Shelby Charger car. Results show that the developed acceleration is 9.49x faster than a traditional (i.e., serial) central processing unit (CPU) MoM implementation, and about 1.66x faster than a parallel six-core CPU MoM implementation. However, in the considered numerical benchmark, the execution of the same computations on the hybrid CPU/FPGA platform reduces the power consumption 2.1x in comparison with the multicore implementation, hence, it allows for the reduction of environmental effects of scientific computing.
引用
收藏
页码:257 / 260
页数:4
相关论文
共 50 条
  • [41] FPGA acceleration of planar multibody dynamics simulations in the Hamiltonian-based divide-and-conquer framework
    Turno, Szymon
    Malczyk, Pawel
    MULTIBODY SYSTEM DYNAMICS, 2023, 57 (01) : 25 - 53
  • [42] Reconfigurable FPGA for network performance evaluation
    Chu, PP
    Jones, RE
    INTERNATIONAL CONFERENCE ON PARALLEL AND DISTRIBUTED PROCESSING TECHNIQUES AND APPLICATIONS, VOLS I-V, PROCEEDINGS, 1999, : 1124 - 1130
  • [43] An FPGA based reconfigurable DDC algorithm
    Juszczyk, B.
    Kasprowicz, G.
    PHOTONICS APPLICATIONS IN ASTRONOMY, COMMUNICATIONS, INDUSTRY, AND HIGH-ENERGY PHYSICS EXPERIMENTS 2016, 2016, 10031
  • [44] FPGA-based reconfigurable computing
    Chang, J. Morris
    Lo, C. Dan
    MICROPROCESSORS AND MICROSYSTEMS, 2006, 30 (06) : 281 - 282
  • [45] FPGA Implementation of Reconfigurable Adaptive Filters
    Shiva, Ajay
    Senthilkumar, E.
    Manikandan, J.
    Agrawal, V. K.
    2017 2ND IEEE INTERNATIONAL CONFERENCE ON WIRELESS COMMUNICATIONS, SIGNAL PROCESSING AND NETWORKING (WISPNET), 2017, : 2544 - 2547
  • [46] FPGA Implementation of Reconfigurable Modulation System
    Mangala, J.
    Manikandan, J.
    2015 INTERNATIONAL CONFERENCE ON ADVANCES IN COMPUTING, COMMUNICATIONS AND INFORMATICS (ICACCI), 2015, : 493 - 500
  • [47] Design of a dedicated reconfigurable multiplier in an FPGA
    Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083, China
    Pan Tao Ti Hsueh Pao, 2008, 11 (2218-2225): : 2218 - 2225
  • [48] RTOS acceleration in an MPSoC with reconfigurable hardware
    Zaykov, Pavel G.
    Kuzmanov, Georgi
    Molnos, Anca
    Goossens, Kees
    COMPUTERS & ELECTRICAL ENGINEERING, 2016, 53 : 89 - 105
  • [49] Reconfigurable Intelligent Instrument Based on FPGA
    Gao, Chengjin
    Sheng, Sheng
    Zhao, Liangliang
    FRONTIERS OF MANUFACTURING AND DESIGN SCIENCE, PTS 1-4, 2011, 44-47 : 767 - 771
  • [50] Reconfigurable digital instrumentation based on FPGA
    Giaconia, C
    Di Stefano, A
    Capponi, G
    3RD IEEE INTERNATIONAL WORKSHOP ON SYSTEM-ON-CHIP FOR REAL-TIME APPLICATIONS, PROCEEDINGS, 2003, : 120 - 122