A 64 channels ASIC for the readout of the silicon strip detectors of the PANDA micro-vertex detector

被引：2

作者：

Mazza, G. ^{[1
]}

Calvo, D. ^{[1
]}

Cossio, F. ^{[1
]}

De Remigis, P. ^{[1
]}

Mignone, M. ^{[1
]}

Wheadon, R. ^{[1
]}

Silvestrin, L. ^{[2
,3
]}

Tessaro, M. ^{[2
]}

机构：

[1] Ist Nazl Fis Nucl, Sez Torino, Via P Giuria 1, I-10125 Turin, Italy

[2] Ist Nazl Fis Nucl, Sez Padova, Via Marzolo 8, I-35121 Padua, Italy

[3] Univ Padua, Via Marzolo 8, I-35121 Padua, Italy

来源：

JOURNAL OF INSTRUMENTATION | 2023年 / 18卷 / 01期

关键词：

Front-end electronics for detector readout; Radiation-hard electronics; VLSI circuits;

D O I：

10.1088/1748-0221/18/01/C01020

中图分类号：

TH7 [仪器、仪表];

学科分类号：

0804 ; 080401 ; 081102 ;

摘要：

The ToASt ASIC is a 64 channel integrated circuit designed for the readout of the double-sided silicon strip sensors that will equip the micro-vertex detector of the PANDA experiment. The ToASt ASIC operates with a 160MHz clock, which defines also the time resolution. A common time stamp is distributed to all channels to provide a common time reference for time of arrival and time over threshold measurements. Two 160 Mb/s serial lines provide the interface to the data concentrator. ToASt is implemented in a commercial 110 nm CMOS technology with triplicated logic to protect against single event upsets.

引用

页数：8

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