共 17 条
- [1] Multi-Size Inverse DCT-II Hardware Design for the VVC Decoder [J]. 2023 IEEE 14TH LATIN AMERICA SYMPOSIUM ON CIRCUITS AND SYSTEMS, LASCAS, 2023, : 68 - 71
- [2] High-Throughput and Low-Power Architectures for the AV1 Arithmetic Encoder [J]. 34TH SBC/SBMICRO/IEEE/ACM SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN (SBCCI 2021), 2021,
- [4] High-Throughput and Multiplierless Hardware Design for the AV1 Fractional Motion Estimation [J]. 2023 IEEE 14TH LATIN AMERICA SYMPOSIUM ON CIRCUITS AND SYSTEMS, LASCAS, 2023, : 72 - 75
- [5] High-Throughput Multifilter VLSI Design for the AV1 Fractional Motion Estimation [J]. 2022 35TH SBC/SBMICRO/IEEE/ACM SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN (SBCCI 2022), 2022,
- [6] High-Throughput and Multiplierless Hardware Design for the AV1 Local Warped MC Interpolation [J]. 2023 IEEE INTERNATIONAL CONFERENCE ON IMAGE PROCESSING, ICIP, 2023, : 2680 - 2684
- [8] A High Throughput Hardware Architecture Targeting the AV1 Paeth Intra Predictor [J]. 2019 IEEE 10TH LATIN AMERICAN SYMPOSIUM ON CIRCUITS & SYSTEMS (LASCAS), 2019, : 93 - 96
- [10] High-Throughput CDEF Architecture for the AV1 Decoder Targeting 4K@60fps Videos [J]. 2020 IEEE 11TH LATIN AMERICAN SYMPOSIUM ON CIRCUITS & SYSTEMS (LASCAS), 2020,