共 50 条
- [1] 3D process integration - Wafer-to-wafer and chip-to-wafer bonding [J]. ENABLING TECHNOLOGIES FOR 3-D INTEGRATION, 2007, 970 : 231 - +
- [2] Chip-to-wafer stacking technology for 3D system integration [J]. 53RD ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, 2003 PROCEEDINGS, 2003, : 1080 - 1083
- [3] Design and Verification of Benzocyclobutene (BCB) Templates for Chip-to-Wafer Alignment in 3D Integration [J]. PROCESSING MATERIALS OF 3D INTERCONNECTS, DAMASCENE AND ELECTRONICS PACKAGING, 2012, 41 (43): : 93 - 102
- [4] Tiny VCSEL Chip Self-Assembly for Advanced Chip-to-Wafer 3D and Hetero Integration [J]. 2014 INTERNATIONAL 3D SYSTEMS INTEGRATION CONFERENCE (3DIC), 2014,
- [5] Cu-Cu Bonding Using Selective Cobalt Atomic Layer Deposition for 2.5-D/3-D Chip Integration Technologies [J]. IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2020, 10 (12): : 2125 - 2128
- [6] New Chip-to-Wafer 3D Integration Technology Using Hybrid Self-Assembly and Electrostatic Temporary Bonding [J]. 2012 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2012,
- [7] Chip-to-Wafer (C2W) 3D Integration with Well-Controlled Template Alignment and Wafer-Level Bonding [J]. 2011 IEEE 61ST ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2011, : 1 - 6
- [8] Technologies for 3D Wafer Level Heterogeneous Integration [J]. DTIP 2008: SYMPOSIUM ON DESIGN, TEST, INTEGRATION AND PACKAGING OF MEMS/MOEMS, 2008, : 123 - +
- [9] Heterogeneous Integration toward Monolithic 3D Chip [J]. 2017 IEEE SOI-3D-SUBTHRESHOLD MICROELECTRONICS TECHNOLOGY UNIFIED CONFERENCE (S3S), 2017,
- [10] Evaluation of Fabrication Process for a Novel Chip-to-Wafer (C2W) 3D Integration Approach Using an Alignment Template [J]. 2012 23RD ANNUAL SEMI ADVANCED SEMICONDUCTOR MANUFACTURING CONFERENCE (ASMC), 2012, : 398 - 403