ANAS: Asynchronous Neuromorphic Hardware Architecture Search Based on a System-Level Simulator

被引：1

作者：

Zhang, Jian ^{[1
]}

Zhang, Jilin ^{[1
]}

Huo, Dexuan ^{[1
]}

Chen, Hong ^{[1
]}

机构：

[1] Tsinghua Univ, Sch Integrated Circuits, Beijing, Peoples R China

来源：

2023 60TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, DAC | 2023年

基金：

中国国家自然科学基金;

关键词：

Neuromorphic Hardware; Architecture Search; System-Level Simulator; Asynchronous Circuit;

D O I：

10.1109/DAC56929.2023.10247850

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

Event-driven asynchronous neuromorphic hardware is emerging for edge computing with high energy efficiency. In order to obtain the architecture with the best hardware performance, we need to search both the numerical and non-numerical design space of asynchronous neuromorphic hardware. However, it is challenging to find an optimal hardware architecture from the non-numerical design space. To address this problem, we propose an asynchronous neuromorphic hardware architecture search (ANAS) method, which uses an evolutionary algorithm to optimize both the numerical and non-numerical design space. Besides, we introduce a configurable asynchronous neuromorphic hardware simulator (CanMore) to offer system-level modeling and performance estimation. Experimental results show that ANAS rivals the best human-designed architecture by 7 x EDP reduction, and offers 2.3 x EDP reduction than the methods that only optimize numerical design space.

引用

页数：6

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