A CAFVF-based output-capacitor-less LDO with PSRR improvement by feed forward and negative capacitance

This paper presents an output-capacitor-less LDO regulator that is implemented in a 0.18 & mu;m CMOS process. It is based on an improved cascode flipped voltage follower that uses two buffer stages to improve loop stability and load current. The feed forward PSRR improvement technique and the equivalent negative capacitance PSRR improvement technique are proposed to improve the power supply rejection ratio (PSRR) performance up to 24 dB at 10 kHz and 38 dB at 100 kHz, respectively. The quiescent current is 27.7 & mu;A, enabling a maximum load current of 50 mA with a dropout voltage of 200 mV. It also achieves excellent line regulation of 0.675 mV/V and load regulation of 8.2 & mu;V/mA.