A Wideband High PSRR Capacitor-Less LDO With Adaptive DC Level Shift and Bulk-Driven Feed-Forward Techniques in 28nm CMOS

被引：0

作者：

Wang, Wei ^{[1
]}

Chi, Baoyong ^{[1
]}

机构：

[1] Tsinghua Univ, Inst Microelect, Beijing, Peoples R China

来源：

2019 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | 2019年

基金：

中国国家自然科学基金;

关键词：

DC level shift; bulk-driven feed-forward; capacitor-less low-dropout regulator; power supply rejection ratio; POWER-SUPPLY-REJECTION; DROP-OUT REGULATOR;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An analog solution of the capacitor-less low dropout regulator (CL-LDO) using the adaptive DC level shift (ADLS) and bulk-driven feed-forward (BDFF) techniques is proposed. The ADLS circuit is adopted to increase the headroom of the pass transistor's gate voltage, which achieves a larger current loading capability without increasing the size of the pass transistor. The BDFF technique decreases the threshold voltage of the pass transistor to improve its current driving capability and expand the bandwidth of the power supply rejection ratio (PSRR) by adding a feed-forward path at the pass transistor's bulk. The proposed LDO has been implemented in TSMC 28nm CMOS. The simulation results show that the proposed CL-LDO consumes 308 mu A current from a 1.2-2.5V power supply, with a 0.7 to 0.9V output range. With 2pF internal capacitance, it can support 0-50mA load current within 80pF load capacitance range. The PSRR is under -20dB across 5MHz frequency range.

引用

页数：5