Reference Thermal Chips for 2D and 3D Co-packaging Process Development

被引：1

作者：

Gupta, Parnika ^{[1
]}

Bernson, Robert ^{[1
]}

Nudds, Noreen ^{[1
]}

Collins, Sean ^{[1
]}

Gradkowski, Kamil ^{[1
]}

Morrissey, Padraic E. ^{[1
]}

O'Brien, Peter ^{[1
]}

机构：

[1] Tyndall Natl Inst, Cork, Ireland

来源：

2023 IEEE 73RD ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE, ECTC | 2023年

关键词：

reference thermal chip; reference PIC; thermal characterization; optical characterization;

D O I：

10.1109/ECTC51909.2023.00372

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We present the concept and experimental realization of reference thermal chips as a way towards standardization of photonic packaging and a method to overcome the cost-barrier for optimization of packaging architectures. The reference thermal chips presented here are tested and co-packaged with reference photonic chips (reference PICs) in 2D and 3D stacked configurations. The effect of thermal dissipation of the reference thermal chip on reference PIC is characterized. This thermal coupling between the chips is then analysed by the measurement of the reference PIC surface temperature in 2D and 3D stacked architectures. The influence of thermal coupling on optical coupling efficiency is evaluated using grating coupler loopback structures on the reference PIC for both configurations. The results describe how such thermal reference chips can be used in the development of new assembly processes for co-packaged electronic and photonic systems.

引用

页码：2160 / 2165

页数：6

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