A negative capacitance FET based energy efficient 6T SRAM computing-in-memory (CiM) cell design for deep neural networks

An Energy-Efficient Computing-in-Memory (CiM) cell design utilizing a Negative Capacitance (NC) FET has been proposed to support computing architectures for Deep Neural Networks (DNNs). The NCFET device characteristics for CiM architectures have been studied to determine an optimal device performance window by changing the thickness of ferroelectric layer (T-fe). The performance metrics such as read margin (RM), write margin (WM), read energy and write energy of NCFET 6 T SRAM cell are analyzed with varying T-fe at two different supply voltages 0.3 V and 0.5 V respectively. NCFET based SRAM cell design achieves higher RM and WM at T-fe of 3 nm and lower energy consumption at 1 nm T-fe as compared with the baseline SRAM cell design at both V-DD = 0.3 V and V-DD = 0.5 V respectively. 6 T NCFET based CiM cell design for performing basic input-weight product operation (IWP) has been demonstrated and performance comparison is done with baseline CMOS design at V-DD = 0.3 V and V-DD = 0.5 V. In comparison with the baseline CMOS CiM cell design, NCFET based SRAM CiM design achieves similar to 2.59x and 1.62x lower energy consumption at V-DD = 0.3 V and V-DD = 0.5 V respectively with an optimal T-fe window of 1-3 nm.