A HOLISTIC STUDY ON METAL PITCH UNIFORMITY CONTROL IN THE SCHEME OF SELF-ALIGNED DOUBLE PATTERNING

被引:0
|
作者
Liu, Zhao [1 ]
机构
[1] Superstring Acad Memory Technol, Beijing, Peoples R China
关键词
D O I
10.1117/12.2685359
中图分类号
O43 [光学];
学科分类号
070207 ; 0803 ;
摘要
The chip size progressive shrinkage imposes more stringent requirement on the fine geometry processing with the technology revolution in the semiconductor industry. Until EUV mass production is available, Self-aligned double patterning (SADP), as well as self-aligned quadruple patterning (SAQP), is the dominate technique applied to achieve smaller Bit Line/Word Line (metal pitch) profile beyond lithography limitation. Conventional metal pitch is formed through Tungsten (W) deposition in the trench after SADP flow, however, the process variation in SADP scheme worsens the metal pitch length uniformity due to Aspect-ratio dependent etching (ARDE) effect. Such metal pitch length nonuniformity directly affects the resistance in the circuit as well as the device performance. Firstly, this paper starts with a deep investigation on the Critical dimension (CD) variation in the traditional SADP scheme from analytical study, followed by the conventional CD control mechanism for individual step. Secondly, it highlights current CD tuning limitation and introduces a novel tuning method. Lastly this paper describes the procedure to build up the new tuning mechanism conceptually and provides applicable suggestions for the industry implementation. Such novel tuning mechanism achieved 32% CD variation reduction.
引用
收藏
页数:4
相关论文
共 50 条
  • [21] Self-Aligned Double and Quadruple Patterning-Aware Grid Routing with Hotspots Control
    Kodama, Chikaaki
    Ichikawa, Hirotaka
    Nakayama, Koichi
    Kotani, Toshiya
    Nojima, Shigeki
    Mimotogi, Shoji
    Miyamoto, Shinji
    Takahashi, Atsushi
    2013 18TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 2013, : 267 - 272
  • [22] Detailed Routing for Spacer-Is-Metal Type Self-Aligned Double/Quadruple Patterning Lithography
    Ding, Yixiao
    Chu, Chris
    Mak, Wai-Kei
    2015 52ND ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC), 2015,
  • [23] Simulation of spacer-based SADP (Self-Aligned Double Patterning) for 15nm half pitch
    Robertson, Stewart
    Wong, Patrick
    Versluijs, Janko
    Wiaux, Vincent
    OPTICAL MICROLITHOGRAPHY XXVI, 2013, 8683
  • [24] Double Self-Aligned Contact Patterning Scheme for 3D Stacked Logic and Memory Devices
    Vincent, B.
    Wen, S.
    Ervin, J.
    ADVANCED ETCH TECHNOLOGY AND PROCESS INTEGRATION FOR NANOPATTERNING XIII, 2024, 12958
  • [25] Litho-Friendly Decomposition Method for Self-Aligned Double Patterning
    Mirsaeedi, Minoo
    Torres, Andres J.
    Anis, Mohab H.
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2013, 21 (08) : 1469 - 1480
  • [26] Cut Optimization for Redundant Via Insertion in Self-Aligned Double Patterning
    Song, Youngsoo
    Hyun, Daijoon
    Lee, Jingon
    Jung, Jinwook
    Shin, Youngsoo
    ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 2019, 24 (06)
  • [27] Recessive Self-aligned Double Patterning with Gap-Fill Technology
    Chen, Yijian
    Xu, Xumou
    Chen, Yongmei
    Miao, Liyan
    Chen, Hao
    Blanco, Pokhui
    Ngai, Chris S.
    OPTICAL MICROLITHOGRAPHY XXIV, 2011, 7973
  • [28] A Self-aligned Double Patterning Technology Using TiN as the Sidewall Spacer
    Chiu, Yuan-Chieh
    Yu, Shu-Sheng
    Hsu, Fang-Hao
    Lee, Hong-Ji
    Lian, Nan-Tzu
    Yang, Tahone
    Chen, Kuang-Chao
    Lu, Chih-Yuan
    2012 23RD ANNUAL SEMI ADVANCED SEMICONDUCTOR MANUFACTURING CONFERENCE (ASMC), 2012, : 332 - 335
  • [29] Redundant via insertion with cut optimization for self-aligned double patterning
    Song, Youngsoo
    Jung, Jinwook
    Shin, Youngsoo
    Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI, 2017, Part F127756 : 137 - 142
  • [30] Redundant Via Insertion with Cut Optimization for Self-Aligned Double Patterning
    Song, Youngsoo
    Jung, Jinwook
    Shin, Youngsoo
    PROCEEDINGS OF THE GREAT LAKES SYMPOSIUM ON VLSI 2017 (GLSVLSI' 17), 2017, : 137 - 142