New partitioned domino circuit for power-efficient wide gates

In this article, a new domino circuit is presented to decrease the power consumption of wide gates without considerable performance and robustness degradation. The suggested circuit technique modifies the output inverter to decrease the switching power by decreasing the voltage swing. Moreover, the wide pull-down net-works can be partitioned into smaller networks. To merge the partitioned pull-down networks, a dynamic NAND gate is employed to increase the circuit performance. Using the proposed technique, the leakage current is decreased in the wide gates because of the stacking effect. Also, the noise immunity is improved due to the body effect. The wide OR gates are simulated in 90-nm CMOS technology. Simulation results show 54% power reduction and 2.55 times improvement in the noise immunity at the same speed in comparison with the con-ventional circuit technique for 64-input OR gates. In addition, a 128-input AND-OR gate is designed using the proposed circuit. Results demonstrate that power and delay are reduced by 39% and 11%, respectively, compared to the conventional AND-OR gate at the same robustness.