gemV-tool: A Comprehensive Soft Error Reliability Estimation Tool for Design Space Exploration

被引:0
|
作者
So, Hwisoo [1 ]
Ko, Yohan [2 ]
Jung, Jinhyo [1 ]
Lee, Kyoungwoo [1 ]
Shrivastava, Aviral [3 ]
机构
[1] Yonsei Univ, Dept Comp Sci, 50 Yonsei Ro, Seoul 03722, South Korea
[2] Yonsei Univ, Div Software, 1 Yonseidae Gil, Wonju 26493, South Korea
[3] Arizona State Univ, Sch Comp Informat & Decis Syst Engn, 660 S Mill Ave, Tempe, AZ 85281 USA
基金
新加坡国家研究基金会;
关键词
soft error; transient fault; fault tolerance; embedded systems; protection technique; MODEL;
D O I
10.3390/electronics12224573
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
With aggressive technology scaling, soft errors have become a major threat in modern computing systems. Several techniques have been proposed in the literature and implemented in actual devices as countermeasures to this problem. However, their effectiveness in ensuring error-free computing cannot be ascertained without an accurate reliability estimation methodology. This can be achieved by using the vulnerability metric: the probability of system failure as a function of the time the program data are exposed to transient faults. In this work, we present a gemV-tool, a comprehensive toolset for estimating system vulnerability, based on the cycle-accurate gem5 simulator. The three main characteristics of the gemV-tool are: (i) fine-grained modeling: vulnerability modeling at a fine-grained granularity through the use of RTL abstraction; (ii) accurate modeling: accurate vulnerability calculation of speculatively executed instructions; and (iii) comprehensive modeling: vulnerability estimation of all the sequential elements in the out-of-order processor core. We validated our vulnerability models through extensive fault injection campaigns with <3% correlation error and 90% statistical confidence. Using the gemV-tool, we made the following observations: (i) the vulnerability of two microarchitectural configurations with similar performance can differ by 82%; (ii) the vulnerability of a processor can vary by more than 10x, depending on the implemented algorithm; and (iii) the vulnerability of each component in the processor varies significantly, depending on the ISA of the processor.
引用
收藏
页数:20
相关论文
共 50 条
  • [1] Hierarchical soft error estimation tool (HSEET)
    Ramakrishnan, K.
    Rajaraman, R.
    Vijaykrishnan, N.
    Xie, Y.
    Irwin, M. J.
    Unlu, K.
    ISQED 2008: PROCEEDINGS OF THE NINTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, 2008, : 680 - +
  • [2] A Comprehensive Soft Error Analysis Tool For Core Networking System
    Zhu, Haihong
    Wong, Rick
    Wen, Shijie
    2013 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), 2013,
  • [3] CARROT - A tool for fast and accurate soft error rate estimation
    Bountas, Dimitrios
    Stamoulis, Georgios I.
    EMBEDDED COMPUTER SYSTEMS: ARCHITECTURES, MODELING, AND SIMULATION, PROCEEDINGS, 2006, 4017 : 331 - 338
  • [4] CODEF: A system level design space exploration tool
    Auguin, M
    Capella, L
    Cuesta, F
    Gresset, E
    2001 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH, AND SIGNAL PROCESSING, VOLS I-VI, PROCEEDINGS: VOL I: SPEECH PROCESSING 1; VOL II: SPEECH PROCESSING 2 IND TECHNOL TRACK DESIGN & IMPLEMENTATION OF SIGNAL PROCESSING SYSTEMS NEURALNETWORKS FOR SIGNAL PROCESSING; VOL III: IMAGE & MULTIDIMENSIONAL SIGNAL PROCESSING MULTIMEDIA SIGNAL PROCESSING - VOL IV: SIGNAL PROCESSING FOR COMMUNICATIONS; VOL V: SIGNAL PROCESSING EDUCATION SENSOR ARRAY & MULTICHANNEL SIGNAL PROCESSING AUDIO & ELECTROACOUSTICS; VOL VI: SIGNAL PROCESSING THEORY & METHODS STUDENT FORUM, 2001, : 1145 - 1148
  • [5] MolTarPred: A web tool for comprehensive target prediction with reliability estimation
    Peon, Antonio
    Li, Hongjian
    Ghislat, Ghita
    Leung, Kwong-Sak
    Wong, Man-Hon
    Lu, Gang
    Ballester, Pedro J.
    CHEMICAL BIOLOGY & DRUG DESIGN, 2019, 94 (01) : 1390 - 1401
  • [6] An FPGA design space exploration tool for matrix inversion architectures
    Irturk, Ali
    Benson, Bridget
    Mirzaei, Shahnam
    Kastner, Ryan
    2008 SYMPOSIUM ON APPLICATION SPECIFIC PROCESSORS, 2008, : 42 - +
  • [7] CAD Tool Design Space Exploration via Bayesian Optimization
    Ma, Yuzhe
    Yu, Ziyang
    Yu, Bei
    2019 ACM/IEEE 1ST WORKSHOP ON MACHINE LEARNING FOR CAD (MLCAD), 2019,
  • [8] An Interactive Design Space Exploration Tool for Dependable Integrated Circuits
    Scharoba, Stefan
    Vierhaus, Heinrich T.
    19TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD 2016), 2016, : 714 - 717
  • [9] Using a Product's Sustainability Space as a Design Exploration Tool
    Mattson, Christopher A.
    Pack, Andrew T.
    Lofthouse, Vicky
    Bhamra, Tracy
    DESIGN SCIENCE, 2019, 5
  • [10] SPACE LAUNCH SYSTEMS COST ESTIMATION AS DESIGN TOOL
    KOELLE, DE
    ACTA ASTRONAUTICA, 1994, 34 : 175 - 181