A Comprehensive Soft Error Analysis Tool For Core Networking System

被引:0
|
作者
Zhu, Haihong [1 ]
Wong, Rick [1 ]
Wen, Shijie [1 ]
机构
[1] Cisco Syst, San Jose, CA 95134 USA
关键词
SEU; Reliability; Mitigation; soft errors;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this paper, we developed a comprehensive single-event upset (SEU) analysis tool. To achieve this goal we start by defining the SEU mitigation strategy as a combination of chip level methods and system level methods. Given a particular SEU chip level and/or system level mitigation choice, we propose first categorizing the SEU Failure In Time (FIT) into different time window bins based on SEU recovery time. Then we analyze the impact of each mitigation strategy, results in the FIT value change in each bin. This tool enables the engineers to do the SEU mitigation design in early design phase. A user-friendly Excel format is also developed to make the complicated model easy to use.
引用
收藏
页数:4
相关论文
共 50 条
  • [1] Handling Soft Error in Embedded Software For Networking System
    Zhu, Haihong Henry
    2014 IEEE INTERNATIONAL SYMPOSIUM ON SOFTWARE RELIABILITY ENGINEERING WORKSHOPS (ISSREW), 2014, : 25 - 28
  • [2] gemV-tool: A Comprehensive Soft Error Reliability Estimation Tool for Design Space Exploration
    So, Hwisoo
    Ko, Yohan
    Jung, Jinhyo
    Lee, Kyoungwoo
    Shrivastava, Aviral
    ELECTRONICS, 2023, 12 (22)
  • [3] A comprehensive error analysis method for the geometric error of multi-axis machine tool
    Chen, Jian-xiong
    Lin, Shu-wen
    Zhou, Xiao-long
    INTERNATIONAL JOURNAL OF MACHINE TOOLS & MANUFACTURE, 2016, 106 : 56 - 66
  • [4] A Comprehensive Soft Error Analysis Methodology for SoCs/ASICs Memory Instances
    Alexandrescu, Dan
    2011 IEEE 17TH INTERNATIONAL ON-LINE TESTING SYMPOSIUM (IOLTS), 2011,
  • [5] SEAT-LA: A soft error analysis tool for combinational logic
    Rajaraman, R
    Kim, JS
    Vijaykrishnan, N
    Xie, Y
    Irwin, MJ
    19TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS, 2005, : 499 - 502
  • [6] A TOOL FOR THE COMPREHENSIVE ANALYSIS OF POWER SYSTEM DYNAMIC STABILITY
    GROSS, G
    IMPARATO, CF
    LOOK, PM
    IEEE TRANSACTIONS ON POWER APPARATUS AND SYSTEMS, 1982, 101 (01): : 226 - 234
  • [7] Hierarchical soft error estimation tool (HSEET)
    Ramakrishnan, K.
    Rajaraman, R.
    Vijaykrishnan, N.
    Xie, Y.
    Irwin, M. J.
    Unlu, K.
    ISQED 2008: PROCEEDINGS OF THE NINTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, 2008, : 680 - +
  • [8] Comprehensive system integration and networking in operating rooms
    Feussner, H.
    Ostler, D.
    Kohn, N.
    Vogel, T.
    Wilhelm, D.
    Koller, S.
    Kranzfelder, M.
    CHIRURG, 2016, 87 (12): : 1002 - 1007
  • [9] An accurate and comprehensive soft error simulator NISES II
    Tosaka, Y
    Satoh, S
    Oka, H
    SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES 2004, 2004, : 219 - 222
  • [10] A Strategy for Soft Error Reduction in Multi Core Designs
    Hyman, Ransford, Jr.
    Bhattacharya, Koustav
    Ranganathan, Nagarajan
    ISCAS: 2009 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-5, 2009, : 2217 - 2220