A Multi-Bit Quantization Low-Latency Voltage Sense Amplifier Applied in RRAM Computing-in-Memory Macro Circuits

被引:1
|
作者
Hu, Wei [1 ]
Zhang, Hangze [1 ]
Wei, Rongshan [1 ]
Chen, Qunchao [1 ]
机构
[1] Fuzhou Univ, Sch Phys & Informat Engn, Fuzhou 350116, Peoples R China
基金
中国国家自然科学基金;
关键词
RRAM; computing-in-memory; voltage sense amplifier; low latency; CMOS;
D O I
10.3390/electronics13020356
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
Conventional sense amplifiers limit the performance of current RRAM computing-in-memory (CIM) macro circuits, resulting in high latency and energy consumption. This paper introduces a multi-bit quantization technology low-latency voltage sense amplifier (MQL-VSA). Firstly, the multi-bit quantization technology enhances circuit quantization efficiency, reducing the number of operational states in conventional VSA. Secondly, by simplifying the sequential logic circuits in conventional VSA, the complexity of sequential control signals is reduced, further diminishing readout latency. Experimental results demonstrate that the MQL-VSA achieves a 1.40-times decrease in readout latency and a 1.28-times reduction in power consumption compared to conventional VSA. Additionally, an 8-bit input, 8-bit weight, 14-bit output macro circuit utilizing MQL-VSA exhibited a 1.11times latency reduction and 1.04-times energy savings.
引用
收藏
页数:16
相关论文
共 28 条
  • [1] An RRAM-Based Digital Computing-in-Memory Macro With Dynamic Voltage Sense Amplifier and Sparse-Aware Approximate Adder Tree
    He, Yifan
    Yue, Jinshan
    Feng, Xiaoyu
    Huang, Yuxuan
    Jia, Hongyang
    Wang, Jingyu
    Zhang, Lu
    Sun, Wenyu
    Yang, Huazhong
    Liu, Yongpan
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2023, 70 (02) : 416 - 420
  • [2] A Multi-bit Near-RRAM based Computing Macro with Highly Computing Parallelism for CNN Application
    Lim, Yujin
    Kim, Dongwhee
    Kim, Jungrae
    2024 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION, DATE, 2024,
  • [3] A Computing-in-memory Scheme with Series Bit-cell in STT-MRAM for Efficient Multi-bit Analog Multiplication
    Hao, Zuolei
    Zhang, Yue
    Wang, Jinkai
    Wang, Hongyu
    Bai, Yining
    Wang, Guanda
    Zhao, Weisheng
    2021 IEEE/ACM INTERNATIONAL SYMPOSIUM ON NANOSCALE ARCHITECTURES (NANOARCH), 2021,
  • [4] A Dual-Wordline 6T SRAM Computing-In-Memory Macro Featuring Full Signed Multi-Bit Computation for Lightweight Networks
    Gu, Zupei
    Dou, Shukao
    You, Heng
    Zhan, Yi
    Qiao, Shushan
    Zhou, Yumei
    IEEE ACCESS, 2024, 12 : 35195 - 35203
  • [5] AND8T SRAM Macro with Improved Linearity for Multi-bit In-Memory Computing
    Sharma, Vishal
    Kim, Ju Eon
    Jo, Yong-Jun
    Chen, Yuzong
    Kim, Tony Tae-Hyoung
    2021 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2021,
  • [6] Compensation of Conductance Mismatch with Redundant Bit-lines for RRAM-based Voltage Sensing Mode Computing-in-Memory
    Gao, Yi
    Wang, Zongwei
    Yu, Zhizhen
    Bao, Lin
    Cai, Yimao
    Huang, Ru
    8TH IEEE ELECTRON DEVICES TECHNOLOGY & MANUFACTURING CONFERENCE, EDTM 2024, 2024, : 412 - 414
  • [7] A 40-nm 118.44-TOPS/W Voltage-Sensing Compute-in-Memory RRAM Macro With Write Verification and Multi-Bit Encoding
    Yoon, Jong-Hyeok
    Chang, Muya
    Khwa, Win-San
    Chih, Yu-Der
    Chang, Meng-Fan
    Raychowdhury, Arijit
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2022, 57 (03) : 845 - 857
  • [8] A Non-volatile Computing-in-Memory ReRAM Macro using Two-bit Current-Mode Sensing Amplifier
    Wu, Qiqiao
    Sun, Wenhao
    Wang, Junpeng
    Bai, Xuefei
    Zhang, Feng
    Chen, Song
    Kang, Yi
    10TH IEEE NON-VOLATILE MEMORY SYSTEMS AND APPLICATIONS SYMPOSIUM (NVMSA 2021), 2021,
  • [9] RRAM Computing-in-Memory Using Transient Charge Transferring for Low-Power and Small-Latency AI Edge Inference
    Wang, Linfang
    An, Junjie
    Ye, Wang
    Li, Weizeng
    Gao, Hanghang
    He, Yangu
    Gao, Jianfeng
    Yue, Jinshan
    Fan, Lingyan
    Dou, Chunmeng
    2022 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, APCCAS, 2022, : 497 - 500
  • [10] A 28-nm RRAM Computing-in-Memory Macro Using Weighted Hybrid 2T1R Cell Array and Reference Subtracting Sense Amplifier for AI Edge Inference
    Ye, Wang
    Wang, Linfang
    Zhou, Zhidao
    An, Junjie
    Li, Weizeng
    Gao, Hanghang
    Li, Zhi
    Yue, Jinshan
    Hu, Hongyang
    Xu, Xiaoxin
    Yang, Jianguo
    Liu, Jing
    Shang, Dashan
    Zhang, Feng
    Tian, Jinghui
    Dou, Chunmeng
    Liu, Qi
    Liu, Ming
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2023, 58 (10) : 2839 - 2850