Multi-objective Floorplanning optimization engaging dynamic programming for system on chip

The quest for optimal VLSI Floorplanning (FP) addressing noteworthy challenges namely Area, Wirelength, and Temperature remains an ongoing field of research. Prevailing FP designs individually optimize these constraints that increase the model complexity with reduced efficiency. Given this motivation, this study provides an optimum FP aimed at minimizing the overall chip area by adhering to the standard design requirements. Accordingly, the divide-and-conquer model of Dynamic Programming (DP) adopted in this work simultaneously optimizes the chip area by devising separate analytical cost functions related to the physical design parameters that are then collated to yield the compact Floor plan. The formulated DP optimization coined as Weighted Aggregated DP-Based FP (WADPFP) adaptively tunes the cost function using rank-sum scaled weights and the discount factor thereby reducing congestion and hotspots. This objective is met using two novel recursive functions ensuring temperature and area scalability. Simulation and synthesis of the proposed FP on the Microelectronic Centre of North Carolina (MCNC) and Gigascale Systems Research Center (GSRC) Benchmark circuits demonstrated the viability of the automated FP design by registering 6.05%, 13%, and 4.35% reduction in area, wirelength, and temperature respectively in comparison with the traditional and recent peers. Additional analysis on the AMI49_X benchmark circuits emphasizes the scalable nature of the introduced WADPFP.