Signal-Division-Aware Analog Circuit Topology Synthesis Aided by Transfer Learning

Compared with conventional analog circuit topology synthesis methods, the deep-reinforcement-learning (DRL)-based method features much higher synthesis efficiency while possessing the merit of strong generalization capability. However, this method cannot synthesize operational amplifiers that involve signal division. To address this critical limitation, this article presents new synthesis rules to guide the DRL-based synthesis process. In addition, to meet various design specifications requested by users, we further develop a smart circuit synthesis system, which can robustly return a solution (i.e., a feasible circuit topology with detailed device sizes) right away as long as the input design specifications are reasonable. A transfer learning (TL) scheme is proposed to reduce the computation overhead of training this system. The experimental results show the efficacy of our smart circuit synthesis system and TL scheme, confirming an advancement over the state-of-the-art approaches.