Parallel Functional Test : A case study to reduce test cost in large SOCs

In modern SOCs, test cost reduction has become a key goal. Test cost contributes to a good part of the die cost and all efforts to minimize the cost are critical to enable good product profit margins and eventually lead to the success of a product. The time taken by each functional test for each IP in the die will contribute to the overall test cost of the SOC. The SOCs contain many design modules integrated into them and testing each of these modules one by one is a tedious and time-consuming process. When we are testing an IP or a group of IPs in the SOC, the rest of the IPs in the chip are in an idle state. Testing all the IPs takes a very long time to cover a single chip, especially on large SOCs. In this paper, we propose a generic solution to reduce the overall test time and hence the test cost. The testing of modules is performed in a simultaneous manner so that at a given time, several IPs can be tested in parallel. We put forth two scenarios of test time optimization. First one being running Memory built-in self-test and Physical layer test in parallel. Second scenario is testing the PLLs across different IPs in a die at the same time. On doing so, in first scenario, we reduce the test time of a die by about 32.43% and about 56.2% using the second one. When this is applied on a large scale on multiple dies, we will be saving a significant amount of time and therefore, improving the cost of testing and profit margins of the product.