FPGA-Based Vehicle Detection and Tracking Accelerator

被引:11
|
作者
Zhai, Jiaqi [1 ]
Li, Bin [1 ,2 ]
Lv, Shunsen [1 ]
Zhou, Qinglei [1 ]
机构
[1] Zhengzhou Univ, Sch Comp & Artificial Intelligence, Zhengzhou 450001, Peoples R China
[2] Henan Key Lab Network Cryptog Technol, Zhengzhou 450001, Peoples R China
关键词
FPGA; vehicle detection; accelerator architecture; YOLO; DeepSort; CNN; SYSTEM;
D O I
10.3390/s23042208
中图分类号
O65 [分析化学];
学科分类号
070302 ; 081704 ;
摘要
A convolutional neural network-based multiobject detection and tracking algorithm can be applied to vehicle detection and traffic flow statistics, thus enabling smart transportation. Aiming at the problems of the high computational complexity of multiobject detection and tracking algorithms, a large number of model parameters, and difficulty in achieving high throughput with a low power consumption in edge devices, we design and implement a low-power, low-latency, high-precision, and configurable vehicle detector based on a field programmable gate array (FPGA) with YOLOv3 (You-Only-Look-Once-version3), YOLOv3-tiny CNNs (Convolutional Neural Networks), and the Deepsort algorithm. First, we use a dynamic threshold structured pruning method based on a scaling factor to significantly compress the detection model size on the premise that the accuracy does not decrease. Second, a dynamic 16-bit fixed-point quantization algorithm is used to quantify the network parameters to reduce the memory occupation of the network model. Furthermore, we generate a reidentification (RE-ID) dataset from the UA-DETRAC dataset and train the appearance feature extraction network on the Deepsort algorithm to improve the vehicles' tracking performance. Finally, we implement hardware optimization techniques such as memory interlayer multiplexing, parameter rearrangement, ping-pong buffering, multichannel transfer, pipelining, Im2col+GEMM, and Winograd algorithms to improve resource utilization and computational efficiency. The experimental results demonstrate that the compressed YOLOv3 and YOLOv3-tiny network models decrease in size by 85.7% and 98.2%, respectively. The dual-module parallel acceleration meets the demand of the 6-way parallel video stream vehicle detection with the peak throughput at 168.72 fps.
引用
收藏
页数:26
相关论文
共 50 条
  • [21] PLACID: A Platform for FPGA-Based Accelerator Creation for DCNNs
    Motamedi, Mohammad
    Gysel, Philipp
    Ghiasi, Soheil
    [J]. ACM TRANSACTIONS ON MULTIMEDIA COMPUTING COMMUNICATIONS AND APPLICATIONS, 2017, 13 (04)
  • [22] FPGA-based Deep Learning Accelerator for RF Applications
    den Boer, H.
    Muller, R. W. D.
    Wong, S.
    Voogt, V.
    [J]. 2021 IEEE MILITARY COMMUNICATIONS CONFERENCE (MILCOM 2021), 2021,
  • [23] An FPGA-based Hardware Accelerator for Simulating Spatiotemporal Neurons
    Tarawneh, Ghaith
    Read, Jenny
    [J]. 2014 21ST IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (ICECS), 2014, : 618 - 621
  • [24] FPGA-Based Accelerator Development for Non-Engineers
    Uliana, David
    Athanas, Peter
    Kepa, Krzysztof
    [J]. 2014 INTERNATIONAL CONFERENCE ON RECONFIGURABLE COMPUTING AND FPGAS (RECONFIG), 2014,
  • [25] A FPGA-based Neural Accelerator for Small IoT Devices
    Hong, Seongmin
    Park, Yongjun
    [J]. PROCEEDINGS INTERNATIONAL SOC DESIGN CONFERENCE 2017 (ISOCC 2017), 2017, : 294 - 295
  • [26] POLAR: A Pipelined/Overlapped FPGA-Based LSTM Accelerator
    Bank-Tavakoli, Erfan
    Ghasemzadeh, Seyed Abolfazl
    Kamal, Mehdi
    Afzali-Kusha, Ali
    Pedram, Massoud
    [J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2020, 28 (03) : 838 - 842
  • [27] Reconfigurable FPGA-based hardware accelerator for embedded DSP
    Rubin, G.
    Omieljanowicz, M.
    Petrovsky, A.
    [J]. MIXDES 2007: Proceedings of the 14th International Conference on Mixed Design of Integrated Circuits and Systems:, 2007, : 147 - 151
  • [28] A reconfigurable FPGA-based spiking neural network accelerator
    Yin, Mingqi
    Cui, Xiaole
    Wei, Feng
    Liu, Hanqing
    Jiang, Yuanyuan
    Cui, Xiaoxin
    [J]. MICROELECTRONICS JOURNAL, 2024, 152
  • [29] The Shunt: An FPGA-Based Accelerator for Network Intrusion Prevention
    Weaver, Nicholas
    Paxson, Vern
    Gonzalez, Jose M.
    [J]. FPGA 2007: FIFTEENTH ACM/SIGDA INTERNATIONAL SYMPOSIUM ON FIELD-PROGRAMMABLE GATE ARRAYS, 2007, : 199 - 206
  • [30] Implementation of FPGA-based Accelerator for Deep Neural Networks
    Tsai, Tsung-Han
    Ho, Yuan-Chen
    Sheu, Ming-Hwa
    [J]. 2019 IEEE 22ND INTERNATIONAL SYMPOSIUM ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS & SYSTEMS (DDECS), 2019,