A 1-V 9.6-GHz charge-pump PLL with low RMS-integrated jitter

被引：2

作者：

Qiu, Ding ^{[1
]}

Kong, Xiangjian ^{[1
]}

Jian, Mingchao ^{[1
]}

Zheng, Jiwei ^{[1
]}

Guo, Chunbing ^{[1
]}

机构：

[1] Guangdong Univ Technol, Sch Informat Engn, Guangzhou, Guangdong, Peoples R China

来源：

MICROELECTRONICS JOURNAL | 2023年 / 142卷

关键词：

Time-amplifying phase-frequency detector; (TAPFD); Phase noise; Jitter; Reference spur; Phase-locked loop (PLL); SUB-SAMPLING PLL; PHASE;

D O I：

10.1016/j.mejo.2023.106006

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A low-power low-jitter phase-locked loop (PLL) with phase noise improvement for radio frequency transceivers is presented in this paper. The in-band phase noise and out-of-band phase noise are both reduced due to the time-amplifying technique and the class-C voltage-controlled oscillator (VCO), respectively. In addition, a low current mismatch charge pump (CP) is used here to guarantee a low reference spur. The proposed PLL is fabricated in a 65-nm CMOS mixed-signal process with an area of 0.220 mm2, and the reference clock is 150 MHz. The mea-surement results show that this PLL operates at 1-V supply voltages and achieves 8.5-10.3-GHz tuning range, 407.807-fs integrated jitter at 9.6 GHz, 7.20-mW total power consumption, resulting in a-239.22-dB figure-of-merit (FoM). The measured reference spur is-51.27 dBc at a 150-MHz offset frequency.

引用

页数：11

共 20 条

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