A Hybrid-PLL (ADPLL/Charge-Pump PLL) Using Phase Realignment With 0.6-us Settling, 0.619-ps Integrated Jitter, and-240.5-dB FoM in 7-nm FinFET

被引：6

作者：

Tsai, Tsung-Hsien ^{[1
,2
]}

Sheen, Ruey-Bin ^{[1
]}

Chang, Chih-Hsien ^{[1
]}

Hsieh, Kenny Cheng-Hsiang ^{[1
]}

Staszewski, Robert Bogdan ^{[3
]}

机构：

[1] Taiwan Semicond Mfg Co, Hsinchu 300, Taiwan

[2] Univ Coll Dublin, Dublin 4, Ireland

[3] Univ Coll Dublin, Sch Elect & Elect Engn, Dublin 4, Ireland

来源：

IEEE SOLID-STATE CIRCUITS LETTERS | 2020年 / 3卷

基金：

爱尔兰科学基金会;

关键词：

All-digital PLL (ADPLL); charge-pump PLL (CP-PLL); fast settling; hybrid PLL; realignment and injection locking; reference spur;

D O I：

10.1109/LSSC.2020.3010278

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

All-digital PLLs (ADPLLs) based on a ring-oscillator (RO) provide very fast settling, but they suffer from quantization noise due to discrete tuning of their digitally controlled oscillator (DCO). Although RO charge-pump PLLs (CP-PLLs) do not exhibit quantization noise thanks to their continuous VCO tuning, they are quite slow and require huge VCO gain to cover frequency drift due to temperature variations. Further, in CP-PLLs, the reset pulse of phase detector (PD) must be wide for proper PLL functioning, but this sets a lower limit on reference spurs. We propose a hybrid-PLL in a 7-nm FinFET CMOS that combines the best advantages of ADPLL and CP-PLL. We introduce periodical phase realignment by the reference clock, and ultrashort pulse for resetting the PD. The hybrid PLL covers 0.2-4 GHz and settles in 0.6 us. It emits low -52 dB reference spurs in the conventional mode, and 1.05 ps and 0.62 ps integrated jitter in the conventional and realignment modes, respectively.

引用

页码：174 / 177

页数：4