Strained Si Nanosheet pFET Based on SiC Strain Relaxed Buffer Layer for High Performance and Low Power Logic Applications

被引：1
|
作者：
Chen, Kun [1 ,2 ]
Yang, Jingwen [1 ]
Wu, Chunlei [1 ,2 ,3 ]
Wang, Chen [1 ,2 ,3 ]
Xu, Min [1 ,2 ,3 ]
Zhang, David Wei [1 ,2 ,3 ]
机构：
[1] Fudan Univ, Sch Microelect, State Key Lab ASIC & Syst, Shanghai 200433, Peoples R China
[2] Shanghai Integrated Circuit Mfg Innovat Ctr Co Ltd, Shanghai 200433, Peoples R China
[3] Zhangjiang Fudan Int Innovat Ctr, Shanghai 200433, Peoples R China
来源：
IEEE ACCESS | 2023年 / 11卷
关键词：
~Gate-all-around (GAA); nanosheet (NS-FET); S/D stressor; stress enhancement; strain relaxed buffer;
D O I：
10.1109/ACCESS.2023.3287148
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
The application of SiC-based strain-relaxed buffers (SRB) technology in gate-all-around (GAA) pMOS nanosheet transistors (NS-FETs) fabrication has been systematically investigated. TCAD simulation results show that SiC SRB can effectively enhance the p-channel stress, up to 3.8Gpa has been achieved without S/D parasitic RC degradation. Furthermore, introducing a wide-bandgap SiC layer underneath NS-FET can help suppress the bottom parasitic transistor. The SiC SRB technology presents a integrated and streamlined approach for addressing the major performance bottlenecks of NS-FETs and is a potential solution for developing future NS-FET based high-performance and low-power logic applications.
引用
收藏
页码：65491 / 65495
页数：5
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