Research on FPGA Accelerator Optimization Based on Graph Neural Network

In this paper, Field Programmable Gate Array (FPGA) hardware structure is designed to accelerate the graph neural network model, and suitable hardware structure is designed for different computing modules to accelerate it, so that the function of the whole system can be improved. The performance of computing intensive applications can be improved by using heterogeneous systems, which are composed of various processor architectures, such as FPGA. Graph Neural Network (GNN) is a framework that uses deep learning to learn graph structure data directly in recent years. Its excellent performance has attracted scholars' high attention and in-depth exploration. By formulating certain strategies on the nodes and edges of the graph, the graph neural network converts the graph structure data into a standard representation, and inputs it into a variety of different neural networks for training. Good results have been achieved in the task of node classification, edge information dissemination and graph clustering.