VLSI Architecture for Image Scaling in Multimedia Applications

被引:0
|
作者
Vivek, C. [1 ]
Gayathri, P. [1 ]
Ranjitha, B. [1 ]
Vibuharshini, M. [1 ]
机构
[1] M Kumarasamy Coll Engn, Dept Elect & Commun Engn, Karur 639113, Tamil Nadu, India
关键词
Digital image processing; Median buffer; Prefilter; De-emphasizing; Picture analysis;
D O I
10.1007/978-981-19-3590-9_33
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
Image scaling is a resizing technique that is frequently used in digital image processing. It is a technique that is used in a variety of fields. The proposed algorithms are implemented in MATLAB for image sampling and ModelSim for hardware architecture processing. The image quality is assessed using the peak signal over noise ratio (PSNR) and structural similarity (SSIM) metrics. The proposed nonlinear picture scaling architecture is straightforward to build and memory-friendly.
引用
收藏
页码:423 / 433
页数:11
相关论文
共 50 条
  • [31] MOTION ESTIMATION VLSI ARCHITECTURE FOR IMAGE-CODING
    PRIVAT, G
    RENAUDIN, M
    PROCEEDINGS - IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN : VLSI IN COMPUTERS & PROCESSORS, 1989, : 78 - 81
  • [33] VLSI IMPLEMENTATION OF A DIGITAL IMAGE THRESHOLD SELECTION ARCHITECTURE
    LIM, PK
    SIDAHMED, MA
    JULLIEN, GA
    INTEGRATION-THE VLSI JOURNAL, 1989, 7 (01) : 77 - 91
  • [34] A VLSI ARCHITECTURE FOR BICUBIC SURFACE PATCH IMAGE GENERATION
    CHAO, PC
    CHERN, MY
    EIGHTH ANNUAL INTERNATIONAL PHOENIX CONFERENCE ON COMPUTERS AND COMMUNICATIONS: 1989 CONFERENCE PROCEEDINGS, 1989, : 54 - 58
  • [35] New image encryption algorithm and its VLSI architecture
    Yen, Jui-Cheng
    Guo, Jiun-In
    IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation, : 430 - 437
  • [36] VLSI Architecture of Spread Sprectrum Image Watermarking Decoder
    Chatterjee, Navonil
    Sohid, Moudud
    Chakraborty, Sudipta
    PROCEEDINGS OF INTERNATIONAL CONFERENCE ON ADVANCES IN COMPUTING, 2013, 174 : 651 - 658
  • [37] A combined VLSI architecture for nonlinear image processing filters
    Hernandez, Orlando J.
    Keohane, Tara
    Steponanko, Julia
    PROCEEDINGS OF THE IEEE SOUTHEASTCON 2006, 2006, : 261 - 266
  • [38] Image Processing VLSI Architecture Based on Data Compression
    Hariyama, Masanori
    Yoshida, Hisashi
    Kameyama, Michitaka
    Kobayashi, Yasubiro
    2008 51ST MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1 AND 2, 2008, : 430 - +
  • [39] VLSI architecture of correlation vector quantization for image coding
    Fudan Univ, Shanghai, China
    Pan Tao Ti Hsueh Pao, 1600, 10 (765-770):
  • [40] VLSI Implementation of an Edge-Oriented Image Scaling Processor
    Chen, Pei-Yin
    Lien, Chih-Yuan
    Lu, Chi-Pin
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2009, 17 (09) : 1275 - 1284