共 50 条
- [2] DIGITAL PHASE-LOCKED LOOP WITH JITTER BOUNDED IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, 1989, 36 (07): : 980 - 987
- [3] Phase-locked loop architecture for adaptive jitter optimization 2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 4, PROCEEDINGS, 2004, : 161 - 164
- [6] Microelectromechanical Phase Detectors for Phase-Locked Loop Applications 2020 IEEE SENSORS, 2020,
- [7] EFFECT OF PHASE JITTER ON PERFORMANCE OF A FIRST-ORDER PHASE-LOCKED LOOP IEEE TRANSACTIONS ON COMMUNICATION TECHNOLOGY, 1970, CO18 (01): : 74 - +
- [8] A Hybrid Phase-Locked Loop for CDR Applications 2011 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2011, : 2533 - 2536
- [9] Frequency jitter of a digital phase-locked loop and comparison with a modified CRB ICCS 2002: 8TH INTERNATIONAL CONFERENCE ON COMMUNICATIONS SYSTEMS, VOLS 1 AND 2, PROCEEDINGS, 2002, : 96 - 100