共 50 条
- [1] DIGITAL PHASE-LOCKED LOOP WITH JITTER BOUNDED [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, 1989, 36 (07): : 980 - 987
- [2] JITTER REDUCTION OF A DIGITAL PHASE-LOCKED LOOP [J]. PROCEEDINGS OF THE IEEE, 1976, 64 (11) : 1640 - 1641
- [3] Phase-locked loop architecture for adaptive jitter optimization [J]. 2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 4, PROCEEDINGS, 2004, : 161 - 164
- [6] Microelectromechanical Phase Detectors for Phase-Locked Loop Applications [J]. 2020 IEEE SENSORS, 2020,
- [7] A Hybrid Phase-Locked Loop for CDR Applications [J]. 2011 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2011, : 2533 - 2536
- [8] EFFECT OF PHASE JITTER ON PERFORMANCE OF A FIRST-ORDER PHASE-LOCKED LOOP [J]. IEEE TRANSACTIONS ON COMMUNICATION TECHNOLOGY, 1970, CO18 (01): : 74 - +
- [9] A low jitter and low-power phase-locked loop design [J]. ISCAS 2000: IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - PROCEEDINGS, VOL II: EMERGING TECHNOLOGIES FOR THE 21ST CENTURY, 2000, : 257 - 260
- [10] Frequency jitter of a digital phase-locked loop and comparison with a modified CRB [J]. ICCS 2002: 8TH INTERNATIONAL CONFERENCE ON COMMUNICATIONS SYSTEMS, VOLS 1 AND 2, PROCEEDINGS, 2002, : 96 - 100