An unconstrained relaxation digital-to-analog converter using optimal bit sequence

被引：0

作者：

Li, Mingze ^{[1
]}

Ma, Guojun ^{[1
]}

Zhang, Long ^{[1
]}

Zhu, Jin ^{[1
]}

Zhu, Qinhua ^{[2
]}

机构：

[1] Jiangsu Univ Sci & Technol, Ocean Coll, Zhenjiang, Jiangsu, Peoples R China

[2] Jiangyin Jiexin Elect Technol Co Ltd, Jiangyin, Peoples R China

来源：

ELECTRONICS LETTERS | 2023年 / 59卷 / 09期

关键词：

circuit optimization; circuits and systems; digital-analogue conversion; intelligent control;

D O I：

10.1049/ell2.12813

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Based on the relaxation digital-to-analog converter (ReDAC) architecture and the capacitor charge/discharge function under discrete time conditions, this paper proposes a new mathematical model for the output voltage of the ReDAC to implement the unconstrained relaxation DAC (Uc-ReDAC). The system clock calibration is not required. An adaptive probabilistic binary particle swarm optimization (AP-BPSO) algorithm is proposed for solving the binary coding configuration problem under the Uc-ReDAC model. Simulation results show that the 8-bit (10-bit) Uc-ReDAC has an average sampling rate of 7.9 MS/s (6.76 MS/s).

引用

页数：3

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