Efficient ATFA design based on CNTFET technology for error-tolerant applications

Today, the main concern of digital circuit designers is reducing the power of portable equipment due to the limitation of charging their batteries. One of the ways to reduce power consumption is to use approximate units in systems that have the ability to tolerate faults. Another solution to consider is designing circuits with Multi-Valued Logic (MVL), which can also reduce power consumption. The use of CNTFET transistors in MVL circuit designs can lead to higher efficiency in integrated circuits, particularly in terms of power, speed and area. Full adders are essential arithmetic modules in processors and serve as the cornerstone of digital systems. In this research study, we aimed to design an Approximate Ternary Full Adder (ATFA) with the minimum number of transistors and power consumption. Based on simulations conducted using Synopsys HSPICE in Stanford's 32 nm CNTFET technology, the proposed ATFA design demonstrated superior performance compared to previous similar designs, particularly in terms of average power consumption, delay, and energy consumption. In addition, according to the examination of noise immunity curves, the proposed circuit has higher pulse noise amplitude in all pulse widths than other circuits. Meanwhile, at the program level, image composition has been considered to study accuracy criteria such as peak Signal-to-Noise Ratio (PSNR), Structural Similarity (SSIM), and Figures Of Merit (FOM) in image synthesis, supported the superior performance of our proposed circuit compared to other similar circuits.